A high-performance unicast configuration scheme for an H-tree based reconfigurable hardware

Reconfigurable computing has attracted considerable attention recently because of the potential to deliver the performance of application-specific hardware along with the flexibility of general-purpose computers. Many reconfigurable architectures have been proposed in the last few years, however, few discussions have been conducted on the specifics of the configuration scheme itself. This paper describes an efficient configuration scheme for a reconfigurable DSP hardware that utilizes a hierarchical interconnection network to link clusters of logic blocks, or cells, to map the desired circuits. The scheme makes use of the hardware´s existing structure and interconnects to communicate configuration data and keeps data path controls simple. The result is a speedy configuration scheme that requires minimal additional control wires and hardware