Title :
High-speed bit-parallel systolic multipliers for a class of GF(2 m)
Author :
Lee, Chiou-Yng ; Lu, Erl-Huei ; Jau-Yien
Author_Institution :
Dept. of Electr. Eng., Chung Gung Univ., Taiwan, China
Abstract :
Two special operations, called the cyclic shifting and the inner product are defined based on the properties of irreducible all one polynomials. With the two operations, an effective algorithm for computing multiplication over a class of GF(2m) was developed in this paper. The low-complexity bit-parallel systolic multipliers are presented. The multiplier is composed of (m+1)2 identical cells, each of which consisting of one 2-bit AND gate, one 2-bit XOR gate and three 1-bit latches. The multiplier has very low latency and propagation delay, which makes them very fast. Moreover the architectures of the multiplier can also be applied to compute multiplication over the class of GF(2m) in which the elements are represented with the root of an irreducible equally spaced polynomial degree
Keywords :
VLSI; digital arithmetic; high-speed integrated circuits; integrated logic circuits; multiplying circuits; parallel algorithms; polynomials; systolic arrays; AND gate; GF(2m) class; XOR gate; bit-parallel systolic multipliers; cyclic shifting operation; high-speed systolic multipliers; inner product operation; latches; low latency; low propagation delay; low-complexity multipliers; multiplication; Computer architecture; Computer science; Cryptography; Digital arithmetic; Electrical engineering; Electrostatic precipitators; Galois fields; Latches; Polynomials; Propagation delay;
Conference_Titel :
VLSI Technology, Systems, and Applications, 2001. Proceedings of Technical Papers. 2001 International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
0-7803-6412-0
DOI :
10.1109/VTSA.2001.934542