DocumentCode :
3254913
Title :
CAD infrastructure for high performance design
Author :
Vercruysse, Ward
fYear :
2001
fDate :
2001
Firstpage :
295
Lastpage :
298
Abstract :
Larger designs and deep submicron effects have fueled an increase in design complexity. First the author describes how these design trends impact his methodology and reports on the growth he experienced as a result. The author then discusses how the CAD environment was setup for the design of the UltraSPARC-III
Keywords :
VLSI; circuit CAD; digital integrated circuits; high level synthesis; integrated circuit design; CAD environment; CAD infrastructure; UltraSPARC-III; deep submicron circuits; design complexity; design methodology; high performance VLSI design; Capacitance; Clocks; Delay; Design automation; Design methodology; Logic; Sun; Timing; Voltage; Wire;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Technology, Systems, and Applications, 2001. Proceedings of Technical Papers. 2001 International Symposium on
Conference_Location :
Hsinchu
ISSN :
1524-766X
Print_ISBN :
0-7803-6412-0
Type :
conf
DOI :
10.1109/VTSA.2001.934543
Filename :
934543
Link To Document :
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