DocumentCode
3254928
Title
New efficient low-complexity architecture for performing inversion and divisions
Author
Liu, Chung-Hsin
Author_Institution
Telecom. Lab., Chunghwa Telecom. Ltd., Taiwan, China
fYear
2001
fDate
2001
Firstpage
299
Lastpage
302
Abstract
In this investigation based on an irreducible all-one polynomial (AOP), we present the proposed inner-product multiplication algorithm. The proposed architecture has a lower per cell circuit complexity and shorter computing delay time than conventional multipliers. Based on the algorithm, we construct the novel inverters and divisors of the cellular architecture. From the point of view of hardware implementation, a dedicated AB2 circuit would be more effective both in constructing an architecture for inversion and division and in constructing an exponentiator in GF(2m)
Keywords
VLSI; cellular arrays; circuit complexity; convolution; delays; digital arithmetic; multiplying circuits; polynomials; GF(2m) finite fields; cellular architecture; circular convolution algorithm; computing delay time; dedicated AB2 circuit; divisions; efficient low-complexity architecture; exponentiator; hardware implementation; inner-product multiplication algorithm; inversion; irreducible all-one polynomial; Circuits; Complexity theory; Computer architecture; Delay effects; Error correction codes; Galois fields; Hardware; Inverters; Polynomials; Telecommunication computing;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, Systems, and Applications, 2001. Proceedings of Technical Papers. 2001 International Symposium on
Conference_Location
Hsinchu
ISSN
1524-766X
Print_ISBN
0-7803-6412-0
Type
conf
DOI
10.1109/VTSA.2001.934544
Filename
934544
Link To Document