Analytical models for estimating parasitic components in power electronics PCBs

Most electromagnetic interference (EMI) problems in power electronics (PE) circuits are strongly related to the parasitic components introduced by printed circuit board (PCB) traces. This influence has been exploited by methods targeting improved EMI performance through a parasitic reduction obtained by appropriate layout transformations. The effectiveness of such methods is highly dependent on the speed and accuracy of the estimators used to quantify the magnitude of parasitic components. This work presents a compilation of analytical models for parasitic estimation in PE circuits based on lumped parameters. Customizations introduced into the base models make possible accommodating features commonly found in PE PCBs while maintaining low computational time requirements for their evaluations. Validation of the developed models with respect to widely accepted parasitic extraction mechanisms reveal that the proposed models create opportunities to develop efficient algorithms for EMI estimation and reduction with feasible running time and limited effect in the accuracy of the estimate