Low overhead correction scheme for unreliable LDPC buffering

Author

Hussien, Amr M. A. ; Elsharkasy, Wael M. ; Eltawil, Ahmed M. ; Kurdahi, Fadi ; Khajeh, Amin

Author_Institution

Electr. Eng. & Comput. Sci. Dept., Univ. of California, Irvine, Irvine, CA, USA

fYear

2013

fDate

3-5 Dec. 2013

Firstpage

667

Lastpage

670

Abstract

Aggressive voltage overscaling (VOS) has been recently adopted to reduce the power consumption of embedded memories. While this affects reliability, several techniques have been developed to achieve reliable operation under aggressive VOS. In this paper, we present a comprehensive power-performance study of LDPC decoders enabling aggressive VOS to internal memories. We propose a correction scheme based on defect map insertion that maintains reliable LDPC decoder under aggressive VOS. The proposed scheme maintains the LDPC decoder performance while achieving a power saving of up to 21%.

Keywords

parity check codes; power aware computing; reliability; aggressive VOS; aggressive voltage overscaling; comprehensive power performance study; defect map insertion; embedded memories; internal memories; low overhead correction scheme; power consumption; power saving; reliability; reliable LDPC decoder; reliable operation; unreliable LDPC buffering; Bit error rate; Decoding; Hardware; Iterative decoding; Noise measurement; Random access memory;

fLanguage

English

Publisher

ieee

Conference_Titel

Global Conference on Signal and Information Processing (GlobalSIP), 2013 IEEE

Conference_Location

Austin, TX

Type

conf

DOI

10.1109/GlobalSIP.2013.6736979

Filename

6736979