Low overhead correction scheme for unreliable LDPC buffering

Aggressive voltage overscaling (VOS) has been recently adopted to reduce the power consumption of embedded memories. While this affects reliability, several techniques have been developed to achieve reliable operation under aggressive VOS. In this paper, we present a comprehensive power-performance study of LDPC decoders enabling aggressive VOS to internal memories. We propose a correction scheme based on defect map insertion that maintains reliable LDPC decoder under aggressive VOS. The proposed scheme maintains the LDPC decoder performance while achieving a power saving of up to 21%.