Designing a clock cleaner with an on-demand digital sigma-delta modulator

We present the design of a digital clock cleaner that reduces clock jitter. Analog phase-locked loops (PLL) are traditionally used to clean clock jitter, but they consume high power and large chip area. A digital solution is more practical because it consumes less power, avoids using large analog components, and covers a wide frequency range. In this paper, we demonstrate a system that measures the instantaneous pulse width of the input clock, finds the average pulse width, and produces a non-jittery clock. We employ a digital sigma-delta modulator to low-pass filter the input pulse count because the DSDM is simple yet provides the narrow bandwidth to compute the average. It is also immune to quantization error and allows fast lock. To reduce power consumption, we activate the filter only when both the input and output counters are ready. We further reduce component count by implementing the DSDM as a three-cycle process. MATLAB- and RTL-level simulation results are presented.