Integration of a low stress photopatternable silicone into a wafer level package

This paper describes a novel wafer level package using a silicone under the bump (SUB) design. The SUB architecture is designed to access the elastomeric qualities of silicones to reduce stresses on solder joints in a chip scale package. Poor reliability of the solder joints frequently arises from stresses generated by the mismatch in coefficient of thermal expansion between the die and the printed circuit board (PCB). Integration of a low modulus silicone pad between the die and solder ball allows for additional deformation mechanisms to dissipate stress between the die and the PCB during thermal cycling, increasing device reliability. Key to the realization of a SUB device was the integration of an elastomeric pad using the recently commercialized Dow Corning^® WL-5150 photodefinable spin-on silicone. SUB devices containing 40 μm thick silicone pads were successfully built using a series of standard processing steps including photolithography, plasma cleaning, and metallization. Two different SUB solder joint designs, suggested by FEA, were constructed and evaluated under thermal cycling. Failure mechanisms in the devices were determined to be dependent on the metallization scheme for the electronic connections. Incorporation of the silicone pads in a SUB device resulted in a 90% increase in reliability relative to control devices without the silicone pad. The failure mechanisms observed suggested an intermediate metallization approach to further enhance reliability.