Evaluation of Futurebus+ for a GMMP multiprocessor

Author

Johnson, Eric E. ; Moore, Roy S. ; Polson, John T.

Author_Institution

Parallel Architecture Res. Lab., New Mexico State Univ., Las Cruces, NM, USA

fYear

1992

fDate

28-30 May 1992

Firstpage

441

Lastpage

444

Abstract

One of the most popular approaches for increasing computer performance is parallel computations using specialized hardware. Clearly, the authors would like to use standardized technology wherever possible in such multiprocessors, in order to minimize the number of unique components that must be (re)designed for each generation of the machine. This paper presents the result of a modelling study that was undertaken to estimate the performance achievable by an implementation of the virtual port memory multiprocessor architecture using the Futurebus+ backplane bus structure. Discrete event simulation and analytical queueing network models concur that peak performance occurs, for typical workloads, at approximately 30 processors on the bus

Keywords

discrete event simulation; message passing; multiprocessing systems; performance evaluation; system buses; Futurebus+ backplane bus structure; analytical queueing network; computer performance; discrete event simulation; global memory message passing multiprocessor; modelling study; parallel computations; virtual port memory multiprocessor architecture; Analytical models; Bandwidth; Computer performance; Concurrent computing; Hardware; Message passing; Parallel architectures; Predictive models; Throughput; Virtual prototyping;

fLanguage

English

Publisher

ieee

Conference_Titel

Computing and Information, 1992. Proceedings. ICCI '92., Fourth International Conference on

Conference_Location

Toronto, Ont.

Print_ISBN

0-8186-2812-X

Type

conf

DOI

10.1109/ICCI.1992.227617

Filename

227617