Title :
A Scalable Packet Sorting Circuit for High-Speed WFQ Packet Scheduling
Author :
McLaughlin, K. ; Sezer, S. ; Blume, H. ; Yang, X. ; Kupzog, F. ; Noll, T.
Author_Institution :
Inst. of Electron., Commun. & Inf. Technol., Queen´´s Univ. Belfast, Belfast
Abstract :
A novel implementation of a tag sorting circuit for a weighted fair queuing (WFQ) enabled IP packet scheduler is presented. The design consists of a search tree, matching circuitry and a custom memory layout. The implementation uses 130 nm silicon technology and supports quality of service on networks at line speeds of 40 Gbps.
Keywords :
IP networks; queueing theory; scheduling; trees (mathematics); IP packet scheduler; custom memory layout; high-speed weighted fair queuing; matching circuitry; quality of service; scalable packet sorting circuit; search tree; Buffer storage; Circuits; Global Positioning System; Hardware; Internet; Processor scheduling; Quality of service; Scheduling algorithm; Sorting; Streaming media;
Conference_Titel :
SOC Conference, 2006 IEEE International
Conference_Location :
Taipei
Print_ISBN :
0-7803-9781-9
Electronic_ISBN :
0-7803-9782-7
DOI :
10.1109/SOCC.2006.283896
