Architectural exploration of high performance Montgomery modular multipliers

Our recently proposed distributed module cluster (DMC) micro-architecture, which is used for long-bit modular multipliers of RSA cryptosystems, is based on a systolic array in which the processing cells are all one-bit long. In the design space exploration of this DMC architecture with TSMC deep sub-micron CMOS standard-cell technology, various widths of processing cells are implemented in the systolic array. The result analysis shows that when the fully serial systolic architecture is used, in which one cell processes one bit, the DMC architecture achieves the highest frequency hence the best performance. If the time and area overhead is represented as time-area product, it is one of the most cost-efficient designs as well