Title :
High-performance energy-efficient memory circuit technologies for sub-45nm technologies
Author :
Agarwal, Amit ; Krishnamurthy, Ram K.
Author_Institution :
Circuit Research Labs, Intel Corporation, Hillsboro, OR 97124, USA
Abstract :
This tutorial discusses challenges and design solutions for high-performance energy efficient memory/register file circuit design. Technology scaling trends for leakage and process variation for sub-45nm technologies are analyzed, with special emphasis on their impact on wide fan in OR gates found in high performance register file. Novel high-speed and leakage/process tolerant circuits are reviewed. Leakage/process sensors which enable these processes compensating techniques are presented.
Keywords :
Active noise reduction; Circuit noise; Circuit synthesis; Decoding; Delay; Energy efficiency; Microprocessors; Noise robustness; Random access memory; Registers;
Conference_Titel :
SOC Conference, 2006 IEEE International
Conference_Location :
Austin, TX
Print_ISBN :
0-7803-9781-9
Electronic_ISBN :
0-7803-9782-7
DOI :
10.1109/SOCC.2006.283907
