Chip-level and Input/Output Interconnects for Gigascale SOCs: Limits and Opportunities

Author

Naeemi, Azad ; Bakir, Muhannad S.

Author_Institution

791 Atlantic Dr. N.W. Atlanta, GA 30332, Georgia Institute of Technology, azad@ece.gatech.edu

fYear

2006

fDate

Sept. 2006

Firstpage

323

Lastpage

324

Keywords

Capacitance; Conductivity; Copper; Crosstalk; Delay; Nanotubes; Optical noise; Power dissipation; Power supplies; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

SOC Conference, 2006 IEEE International

Conference_Location

Austin, TX

Print_ISBN

0-7803-9781-9

Electronic_ISBN

0-7803-9782-7

Type

DOI

10.1109/SOCC.2006.283908

Filename

4063077

Link To Document