Title :
A high-efficiency 5-GHz-band SOI power MOSFET having a self-aligned drain offset structure
Author :
Matsumoto, Satoshi ; Hiraoka, Yasushi ; Sakai, Tatsuo
Author_Institution :
NTt Telecommun. Energy Labs., Kanagawa, Japan
Abstract :
A highly efficient RF thin-film SOI power MOSFET having a self-aligned offset gate structure is proposed. It was fabricated using a self-aligned offset gate structure based on an LDD structure to reduce the on-resistance and thus increase the power-added efficiency. The target breakdown voltage was 10 V, and the fabricated device has a breakdown voltage of 14.3 V. The RF performances of the proposed power MOSFET are the acceptable for both the 2 and 5 GHz-bands. The linear amplification characteristics of the SOI power MOSFET are almost the same as those of compound semiconductor devices
Keywords :
power MOSFET; silicon-on-insulator; 10 V; 14.3 V; 2 GHz; 5 GHz; LDD structure; fabricated device; high-efficiency 5-GHz-band SOI power MOSFET; linear amplification characteristics; on-resistance; power-added efficiency; self-aligned drain offset structure; self-aligned offset gate structure; target breakdown voltage; Integrated circuit technology; Laboratories; MMICs; MOSFET circuits; Power MOSFET; Radio frequency; Semiconductor devices; Silicon; Substrates; Transistors;
Conference_Titel :
Power Semiconductor Devices and ICs, 2001. ISPSD '01. Proceedings of the 13th International Symposium on
Conference_Location :
Osaka
Print_ISBN :
4-88686-056-7
DOI :
10.1109/ISPSD.2001.934566
