A new phase-locked loop with high speed phase frequency detector

In this paper, we first systematically analyze existing phase frequency detectors from aspects of theoretical analysis and circuit operation. Based on the circuit architecture, both classifications and comparisons are made. Then we propose a high speed phase frequency detector for PLL design. The proposed phase frequency detector is simple in its structure and has no glitch output as well as better phase characteristics. Furthermore, some simulations results by HSPICE are performed based on 0.35 mum process parameters. Several prior art phase frequency detectors with the proposed one are compared for phase sensitivity, dead zone characteristics and maximum operation frequency. Based on simulation results, the proposed phase frequency detector shows satisfactory circuit performance with higher operation frequency, lower phase jitter and smaller circuit complexity. The speed of the proposed phase frequency detector is up to 3.5GHz. Moreover, the circuit design of a GHz PLL has been completed including high speed VCO, charge pump and phase frequency detector with an external loop filter. The total layout size excluding pads is 216.3mum times 47.85mum. The post-layout simulations for 1.1 GHz PLL loop operation has been shown and verified