DSP-RAM: A logic-enhanced memory architecture for communication signal processing

Author

Wang, Zixiong ; Cockburn, Bruce F. ; Elliott, Duncan G. ; Krzymien, Witold A.

Author_Institution

Dept. of Electr. & Comput. Eng., Alberta Univ., Edmonton, Alta., Canada

fYear

1999

fDate

1999

Firstpage

475

Lastpage

478

Abstract

In this paper a new parallel computational RAM (C·RAM) architecture, called DSP-RAM, is proposed to speed up a class of digital signal processing (DSP) algorithms in telecommunications. The proposed architecture integrates memory and single instruction stream, multiple data stream (SIMD) parallel processing into a single chip. Key elements of the architecture were designed to verify their cost in silicon area. A software simulator was written in C++ to evaluate the performance of DSP-RAM implementations of critical components in the ITU G.728 voice coding standard

Keywords

digital signal processing chips; parallel architectures; parallel memories; random-access storage; C·RAM; DSP-RAM; ITU G.728 voice coding standard; SIMD parallel processing; communication signal processing; digital signal processing; logic-enhanced memory architecture; parallel computational RAM architecture; Computer architecture; Concurrent computing; Costs; Digital signal processing chips; Memory architecture; Parallel processing; Random access memory; Read-write memory; Signal processing algorithms; Telecommunication computing;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications, Computers and Signal Processing, 1999 IEEE Pacific Rim Conference on

Conference_Location

Victoria, BC

Print_ISBN

0-7803-5582-2

Type

conf

DOI

10.1109/PACRIM.1999.799579

Filename

799579