A novel process technique for fabricating high reliable trench DMOSFETs using self-align technique and hydrogen annealing

Author

Kim, Jongdae ; Roh, Tae Moon ; Kim, Sang-Gi ; Lee, Dae Woo ; Koo, Jin Gun ; Cho, Kyoung-Ik

Author_Institution

Micro-Electron. Technol. Lab., Electron. & Telecommun. Res. Inst., Daejeon, South Korea

fYear

2001

fDate

2001

Firstpage

139

Lastpage

142

Abstract

A novel process technique for fabricating trench DMOSFETs using 3 mask layers is realized in order to obtain cost-effective production capability, higher cell density and current driving capability, and higher reliability. A unit cell with a cell pitch of 2.3~2.4 μm and a channel density of 100 Mcell/in² are obtained. Specific on-resistance is 0.36 mΩ.cm² with a blocking voltage of 43 V. The time to breakdown of gate oxide grown on the hydrogen annealed trench surface is much longer than that of the gate oxide grown on the non-hydrogen annealed trench surface

Keywords

annealing; power MOSFET; semiconductor device breakdown; semiconductor device reliability; 43 V; blocking voltage; cell density; current driving; fabrication process; gate oxide; hydrogen annealing; mask layer; power MOSFET; reliability; self-aligned technique; specific on-resistance; time-to-breakdown; trench DMOSFET; Annealing; Breakdown voltage; CMOS technology; Etching; Hydrogen; Ion implantation; MOSFETs; Oxidation; Silicon; Surface resistance;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Semiconductor Devices and ICs, 2001. ISPSD '01. Proceedings of the 13th International Symposium on

Conference_Location

Osaka

ISSN

1063-6854

Print_ISBN

4-88686-056-7

Type

conf

DOI

10.1109/ISPSD.2001.934575

Filename

934575