A 2.7-/spl mu/W/MHz transmission-gate-based 16-bit multiplier for digital hearing aids

Various 16-bit multiplier architectures are compared in terms of dissipated energy, EDP (energy-delay product), and area occupation, in view of low-power low-voltage signal processing for digital hearing aids and similar applications. It is found that the propagation of glitches along uneven and reconvergent paths results in large unproductive node activity. Because of their shorter full-adder chains, Wallace-tree multipliers indeed dissipate less energy than the carry-save and other traditional array multipliers (5.4 to 6.1muW/MHz versus 9.4muW/MHz and more for 0.25mum CMOS technology at 0.75 V). By combining the Wallace-tree architecture with transmission gates, a new approach is proposed to further improve the energy-efficiency (2.7muW/MHz), beyond recently published low-power architectures. Beside the reduction of the overall capacitance, transmission gate full-adders act as RC-low-pass filters that attenuate undesired switching