Large area 4H-SiC power MOSFETs

This paper describes the design and fabrication of 4H-SiC, n-channel Power MOSFETs. For the first time, we have achieved 350 V, 10 A (V_F=4.4 V) devices with an active area of 0.105 cm² (3.3 mm ×3.3 mm). This represents a specific on-resistance of 43 mΩ·cm² for a cell pitch of 25 μm (160,000 cells/cm²). We have also achieved R_on,sp=23 mΩ·cm² on smaller cells with a cell pitch of 16 μm (390,000 cells/cm²). An important issue in 4H-SiC MOSFETs is extremely low effective channel mobility (μ_neff) in the implanted p-well regions. It is shown that Al-implanted p-wells require at least 1600°C activation anneal to achieve reasonable bulk hole mobility. Annealing at high temperatures causes surface roughness which degrades μ_neff compared to low power MOSFETs made on a p-epilayer. NO annealing of the gate oxide and a buried channel structure are used for increasing μ _neff. A Buried channel (BC) structure with 1.7×10¹² cm^-2 charge in the channel showed a high μ_neff (195 cm²/V·s) utilizing bulk buried channel, but resulted in a normally-on device. However, it is shown that by controlling the charge in the BC layer, a normally-off device with a high μ_neff can be produced