An assessment of high-level partitioning techniques for implementing discrete signal transforms on distributed hardware architectures

Partitioning is an essential step in the implementation of algorithms to distributed hardware architectures (DHAs) such as multi-FPGA boards. While numerous approaches working at the structural level have been reported, techniques targeted at higher levels are less common. Moreover, when dealing with discrete signal transforms (DSTs), formulation-level partitioners for DHAs have been largely neglected. In this paper, we introduce a first approach towards a functionally-aware methodology that could provide improved results for the high-level partitioning of DSTs to DHAs. Our methodology has been devised through the study of DST partitioning techniques for DHA-similar systems, as well as general DST formulation techniques. An assessment performed on discrete Fourier transforms has achieved as much as 35% in latency reduction when compared to other general, high-level partitioning schemes