DocumentCode
3255751
Title
A RISC core design for an ATM network interfaces
Author
Elkateeb, A. ; Elbeshti, M.
Author_Institution
Jodrey Sch. of Comput. Sci., Acadia Univ., Wolfville, NS, Canada
fYear
1999
fDate
1999
Firstpage
564
Lastpage
567
Abstract
The embedded RISC core can be used efficiently to design high-speed scalable ATM network interfaces. Such core could also make the design of these interfaces simple, shorten the developing cycle and reduce their developing cost. In this paper, we have studied the design issues related to reduced instruction set computer (RISC) core and specifically for high-speed ATM host-network interfaces applications. We have investigated the processing and the instruction types that the RISC core is usually performed in addition to its structure
Keywords
asynchronous transfer mode; hardware description languages; network interfaces; pipeline processing; reduced instruction set computing; ATM network interfaces; VHDL based simulation; developing cost; developing cycle; instruction types; pipelined RISC core design; Application software; Clocks; Computer aided instruction; Costs; Design optimization; Hardware; High-speed networks; Logic; Network interfaces; Reduced instruction set computing;
fLanguage
English
Publisher
ieee
Conference_Titel
Communications, Computers and Signal Processing, 1999 IEEE Pacific Rim Conference on
Conference_Location
Victoria, BC
Print_ISBN
0-7803-5582-2
Type
conf
DOI
10.1109/PACRIM.1999.799600
Filename
799600
Link To Document