Block placement for reduced delay uncertainty in high performance clock distribution networks

Uncertainty in the delay of the clock signal is introduced by a number of factors that affect the clock distribution network, examples of which include process and environmental parameter variations and interconnect noise. The more strict the setup and hold time constraints of a combinational data path, the more sensitive the timing of a data path is to delay uncertainty. A design methodology to reduce the delay uncertainty of the clock signal, particularly at the most critical data paths within a system is presented in this paper. A placement algorithm is utilized that is based on the sequence-pair placement representation which determines the minimal placement area for a set of circuit blocks. The sequence-pair placement approach is modified to prioritize the placement of the blocks containing the critical registers of a circuit. The cost function for placement is also modified. Alternatively to minimal area, the placement objective for the critical blocks is to minimize the non-common portion of the clock tree among the registers of the critical blocks. Once the placement of the critical blocks is determined, the remaining blocks in a circuit are being placed. The proposed methodology is applied to a set of benchmark circuits. It is demonstrated that a reduction of up to 77% on the non-common portion among the critical clock paths can be achieved. The tradeoff of this approach is an increase of up to 9% in the total circuit area