DocumentCode :
3255841
Title :
Analysis and implementation of a VLSI neural network
Author :
Cardarilli, G.C. ; Di Stefano, G. ; Fabrizi, G. ; Marinucci, P.
Author_Institution :
Dipartimento di Ingegneria Elettrica, l´´Aquila Univ., Italy
Volume :
3
fYear :
1995
fDate :
Nov/Dec 1995
Firstpage :
1482
Abstract :
Hardware implementation of programmable neural networks requires the availability of a device where the synaptic value will be stored. This value can be represented either by an analog voltage or by using a digital word. Both cases imply that synaptic values are bounded with strong consequences for the network performances. Hence an architecture design of a neural network cannot prescind from a deep analysis on the limits due to the hardware implementation. In the first part of this article the authors explore the consequences of such limitations on a single neuron, then they extend the results on a network. In the second part the authors describe a very efficient implementation of programmable neural networks based on a CMOS operational transconductance amplifier (OTA), which takes in account the results achieved during the theoretical analysis
Keywords :
CMOS integrated circuits; VLSI; neural chips; neural net architecture; operational amplifiers; CMOS operational transconductance amplifier; VLSI neural network; analog voltage; architecture design; digital word; programmable neural networks; synaptic value; Availability; Feedforward neural networks; Neural network hardware; Neural networks; Neurons; Operational amplifiers; Real time systems; Transconductance; Very large scale integration; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Neural Networks, 1995. Proceedings., IEEE International Conference on
Conference_Location :
Perth, WA
Print_ISBN :
0-7803-2768-3
Type :
conf
DOI :
10.1109/ICNN.1995.487380
Filename :
487380
Link To Document :
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