Analysis and implementation of a VLSI neural network

Hardware implementation of programmable neural networks requires the availability of a device where the synaptic value will be stored. This value can be represented either by an analog voltage or by using a digital word. Both cases imply that synaptic values are bounded with strong consequences for the network performances. Hence an architecture design of a neural network cannot prescind from a deep analysis on the limits due to the hardware implementation. In the first part of this article the authors explore the consequences of such limitations on a single neuron, then they extend the results on a network. In the second part the authors describe a very efficient implementation of programmable neural networks based on a CMOS operational transconductance amplifier (OTA), which takes in account the results achieved during the theoretical analysis