Design, simulation and synthesis of a 32-bit math-processor

Author

Ardalan, Shahab ; Adibi, Akbar

Author_Institution

Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont.

fYear

2005

fDate

7-10 Aug. 2005

Firstpage

1469

Abstract

This paper presented the design and results of simulation and synthesis of a 32-bit math-processor. The emphasis was placed on implementation of floating-point arithmetic unit. This math-processor is designed in fully behavioral level by using VHDL and is able to perform floating-point operation on double precision. Also as nature of behavioral description, it is easy to convert the precision to 64-bit or more. The main ALU includes four separate ALUs: sign ALU, integer number ALU, mantissa and exponent ALU (for real number). This processor uses the micro-controlling method for control unit. This behavioral design is synthesis-able and ready for layout and fabrication or FPGA based digital circuits. Synthesis was done by Leonardo Exemplar tool and it shows this design includes 27000 standard cells and can work on 40 MHz clock in 1mum CMOS technology

Keywords

CMOS digital integrated circuits; floating point arithmetic; integrated circuit design; microprocessor chips; 1 micron; 32 bit; 40 MHz; ALU; CMOS technology; FPGA based digital circuits; Leonardo Exemplar tool; VHDL; control unit; floating-point arithmetic unit; math-processor; microcontrolling method; CMOS technology; Central Processing Unit; Circuit synthesis; Computational modeling; Computer aided instruction; Computer simulation; Design engineering; Fabrication; Floating-point arithmetic; Hardware;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2005. 48th Midwest Symposium on

Conference_Location

Covington, KY

Print_ISBN

0-7803-9197-7

Type

conf

DOI

10.1109/MWSCAS.2005.1594390

Filename

1594390