An IC design for real-time motion estimation for H.264 digital video

Author

Hsu, Kenneth W. ; Li, Xiang ; Chopra, Rahul

Author_Institution

Dept. of Comput. Eng., Rochester Inst. of Technol.

fYear

2005

fDate

7-10 Aug. 2005

Firstpage

1489

Abstract

An IC design to achieve real-time motion estimation compensation encoding for H.264 ITU video compression standard is presented. A full-search block matching algorithm has been adapted to a pipelined data flow to enable parallel processing of variable block sized block matching and fractional pixel motion vector generation. High definition TV (HDTV) requires wide bandwidth and a large amount of memory for digital video processing. The SOC is designed with TSMC 0.18mum technology using VHDL and optimized to achieve a 125 MHz clock speed to make real-time processing possible

Keywords

data compression; high definition television; integrated circuit design; motion compensation; motion estimation; real-time systems; system-on-chip; video coding; 125 MHz; H.264 digital video; HDTV; ITU video compression standard; VHDL; digh definition TV; digital video processing; fractional pixel motion vector generation; full-search block matching algorithm; integrated circuit design; parallel processing; pipelined data flow; real-time motion compensation encoding; real-time motion estimation; system-on-chip; variable block sized block matching; Bandwidth; Design optimization; Digital integrated circuits; Encoding; HDTV; High definition video; Motion estimation; Parallel processing; TV; Video compression;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2005. 48th Midwest Symposium on

Conference_Location

Covington, KY

Print_ISBN

0-7803-9197-7

Type

conf

DOI

10.1109/MWSCAS.2005.1594395

Filename

1594395