Title :
60 V field NMOS and PMOS transistors for the multi-voltage system integration
Author :
Terashima, Tomohide ; Yamamoto, Fumitoshi ; Hatasako, Kenichi ; Hine, Shiro
Author_Institution :
ULSI Dev. Center, Mitsubishi Electr. Corp., Hyogo, Japan
Abstract :
60 V field NMOS and PMOS transistors have been developed on the standard 0.5 μm BiC-DMOS process without any additional process steps. Both of the devices handle 60 V input voltage on every electrode, and have excellent current stability. Therefore, the devices have sufficient capability for 60 V class level shifting and accurate voltage sensing. In particular, 60 V field NMOS with a negative threshold voltage has realized voltage sensing in the range from zero to 60 V, which is a novel function for HVIC
Keywords :
BIMOS integrated circuits; circuit stability; power MOSFET; power integrated circuits; 0.5 mum; 60 V; 60 V class level shifting; BiC-DMOS process; HVIC; NMOS transistors; PMOS transistors; accurate voltage sensing; current stability; input voltage; multi-voltage system integration; negative threshold voltage; BiCMOS integrated circuits; Displays; Driver circuits; Electrodes; Epitaxial layers; MOS devices; MOSFETs; Standards development; Threshold voltage; Ultra large scale integration;
Conference_Titel :
Power Semiconductor Devices and ICs, 2001. ISPSD '01. Proceedings of the 13th International Symposium on
Conference_Location :
Osaka
Print_ISBN :
4-88686-056-7
DOI :
10.1109/ISPSD.2001.934604
