Title :
Power BiCMOS process with high voltage device implementation for 20 V mixed signal circuit applications
Author :
Nehrer, W. ; Anderson, L. ; Debolske, T. ; Efland, T. ; Fleischmann, P. ; Haidinyak, C. ; Leitz, W. ; McNutt, M. ; Mindricelu, E. ; Pendharkar, S. ; Smith, J. ; Taylor, R.V.
Author_Institution :
Texas Instrum. Inc., Santa Cruz, CA, USA
Abstract :
Optimization of circuit performance and cost generally involves a trade-off between a) circuit design and die area efficiency plus shortest time to market with b) maintaining production efficiency of multiple process variants with multiple component lists. Key technology drivers were identified and redesigned in the LBC6 generation power BiCMOS process described herein to achieve a 40% die area reduction for the huge 20 V and below power IC application market. In this paper, we discuss components and their design, generic process flow, and reasoning
Keywords :
BiCMOS integrated circuits; circuit optimisation; integrated circuit design; mixed analogue-digital integrated circuits; power MOSFET; power integrated circuits; 20 V; 20 V mixed signal circuit applications; LBC6 generation power BiCMOS process; circuit design; circuit performance optimization; cost optimization; die area efficiency; die area reduction; generic process flow; high voltage device implementation; multiple component lists; multiple process variants; power BiCMOS process; power IC application market; production efficiency; shortest time to market; BiCMOS integrated circuits; Circuit optimization; Circuit synthesis; Cost function; Design optimization; Driver circuits; Optimized production technology; Power generation; Time to market; Voltage;
Conference_Titel :
Power Semiconductor Devices and ICs, 2001. ISPSD '01. Proceedings of the 13th International Symposium on
Conference_Location :
Osaka
Print_ISBN :
4-88686-056-7
DOI :
10.1109/ISPSD.2001.934605
