A VLSI processor-switch for a dual IEEE-796 bus with shared and dual-port memories

The authors have developed a VLSI switch which controls and arbitrates the signals of a double multibus (IEEE-796 standard) system. There is one switch per processor, which is placed between the processor and the buses. Besides the pure shared-memory accesses, the switch also recognizes requests for another processor´s dual-port memory and routes the data transfer accordingly. The chip was design with Silver Lisco CAD software and simulated using HILO-3 development tools. A detailed simulation of the standard cells was possible using a library of gate-level models with the appropriate timing characteristics. Functional models of the processor and the memories, together with the gate-level switch model, provided a complete dynamic simulation of the multiprocessor system. The simulation allows a full check of the VLSI component, including a functional description of processor and memories, before the manufacturing process