Title :
The scalable processor architecture (SPARC)
Author :
Garner, R.B. ; Agrawal, A. ; Briggs, F. ; Brown, E.W. ; Hough, D. ; Joy, B. ; Kleiman, S. ; Muchnick, S. ; Namjoo, M. ; Patterson, D. ; Pendleton, J. ; Tuck, Richard
Author_Institution :
Sun Microsyst. Inc., Mountain View, CA, USA
fDate :
Feb. 29 1988-March 3 1988
Abstract :
An introduction is given to the SPARC architecture and its more interesting features. The discussion covers the registers (both window and floating-point), and instructions, including formats, load/store, integer computation, control transfer, floating-point computation, and coprocessor. A brief comparison with Berkeley RISC (reduced-instruction-set-computer) and SOAR is provided.<>
Keywords :
parallel architectures; Berkeley RISC; SOAR; SPARC architecture; control transfer; coprocessor; floating-point computation; formats; instructions; integer computation; load/store; reduced-instruction-set-computer; registers; scalable processor architecture; window; Application software; CMOS process; Computer architecture; Coprocessors; Costs; Floating-point arithmetic; Integrated circuit technology; Reduced instruction set computing; Registers; Sun;
Conference_Titel :
Compcon Spring '88. Thirty-Third IEEE Computer Society International Conference, Digest of Papers
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-8186-0828-5
DOI :
10.1109/CMPCON.1988.4874
