Optimization methodology of global interconnect structure

Author

Inoue, Junpei ; Nakashima, Hidenari ; Kyogoku, Takanori ; Uezono, Takumi ; Okada, Kenichi ; Masu, Kazuya

Author_Institution

Precision & Intelligence Lab., Tokyo Inst. of Technol., Yokohama, Japan

fYear

2004

fDate

6-8 Dec. 2004

Firstpage

351

Lastpage

354

Abstract

The optimal interconnect structure is required because circuit performance depends on resistance and capacitance in interconnects. This paper proposes the optimization methodology of interconnect structure based on the wire length distribution (WLD) model. Using the proposed method, metal height and ILD thickness of global interconnect layer in 65 nm node become larger than the ITRS structure. Compared with the ITRS structure, the delay time can be improved by 9% and 22% for complex and simple circuits, respectively.

Keywords

circuit optimisation; integrated circuit design; integrated circuit interconnections; integrated circuit modelling; 65 nm; International Technology Roadmap for Semiconductors; capacitance; delay time; interconnect layer; interconnect structure; optimization method; resistance; wire length distribution model; Capacitance; Circuit optimization; Delay effects; Design methodology; Integrated circuit interconnections; Large scale integration; Optimization methods; Pins; Predictive models; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics, 2004. ICM 2004 Proceedings. The 16th International Conference on

Print_ISBN

0-7803-8656-6

Type

conf

DOI

10.1109/ICM.2004.1434584

Filename

1434584