Title :
New benchmark for RESURF, SOI and super-junction power devices
Author_Institution :
Consumer Syst., Philips Semicond., Nijmegen, Netherlands
Abstract :
This article will establish theoretical limits of the on-resistance for for different power-semiconductor technologies by analyzing their ionization integral. The quality of this benchmark is reviewed with previously published data. A good correlation is obtained despite the clearly stated simplifications. Apparently, a 4-fold margin between theory and practice covers process spread and parasitic resistive elements
Keywords :
impact ionisation; power semiconductor devices; silicon-on-insulator; DMOS device; RESURF power device; SOI power device; impact ionization; on-resistance; parasitic resistive element; power semiconductor technology; process spread; super-junction power device; Electric resistance; Immune system; Impact ionization; Insulated gate bipolar transistors; Semiconductor device doping; Semiconductor diodes; Silicon on insulator technology; Surface resistance; Voltage; Wiring;
Conference_Titel :
Power Semiconductor Devices and ICs, 2001. ISPSD '01. Proceedings of the 13th International Symposium on
Conference_Location :
Osaka
Print_ISBN :
4-88686-056-7
DOI :
10.1109/ISPSD.2001.934625
