DocumentCode
3256509
Title
Efficient construction of catastrophic patterns for VLSI reconfigurable arrays with bidirectional links
Author
Nayak, Amiya ; Pagli, Linda ; Santoro, Nicola
Author_Institution
Center for Parallel & Distributed Comput., Carleton Univ., Ottawa, Ont., Canada
fYear
1992
fDate
28-30 May 1992
Firstpage
79
Lastpage
83
Abstract
Patterns of faults that are catastrophic for regular architectures, particularly the systolic arrays, have been studied. For a given link configuration, there are many fault patterns which are catastrophic. Among those, there is a particular fault pattern, called the reference fault pattern, which is crucial for the development of testing techniques; furthermore, the efficiency of any testing algorithm can be further improved in the presence of efficient algorithms for constructing the reference fault pattern. The authors develop a new algorithm for the construction of the reference fault pattern for VLSI reconfigurable arrays in which the links are bidirectional. The complexity of the new algorithm is O (kN ) which is a significant improvement over the existing O (N 2 ) algorithm, where k is the number of bypass links, and N is the length of the largest bypass link
Keywords
VLSI; computational complexity; logic testing; reconfigurable architectures; systolic arrays; VLSI; bidirectional links; bypass links; catastrophic fault patterns; link configuration; reconfigurable arrays; reference fault pattern; systolic arrays; testing algorithm; Clustering algorithms; Computer science; Distributed computing; Fault diagnosis; Fault tolerance; Redundancy; Sufficient conditions; System testing; Systolic arrays; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Computing and Information, 1992. Proceedings. ICCI '92., Fourth International Conference on
Conference_Location
Toronto, Ont.
Print_ISBN
0-8186-2812-X
Type
conf
DOI
10.1109/ICCI.1992.227700
Filename
227700
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