Title :
Enhancing ESys.Net with a semi-formal verification layer
Author :
Gorse, N. ; Metzger, M. ; Lapalme, J. ; Aboulhamid, E.M. ; Savarie, Y. ; Nicolescu, G.
Author_Institution :
Montreal Univ., Que., Canada
Abstract :
As electronic systems reach tremendous complexity, new CAD tools are needed to cope with their design and verification. ESys.Net, a new design environment under development at Universite de Montreal proposes an elegant solution for modeling and simulation. This paper presents the extension of this environment with a complete verification layer based on linear temporal logic. This is a major enhancement to ESys.Net, since it allows designers to use it not only for modeling and simulation but also for verification.
Keywords :
formal verification; logic CAD; temporal logic; CAD tools; ESys.Net; electronic system; linear temporal logic; semiformal verification layer; Design automation; Fabrication; Hardware design languages; Investments; Logic; Memory management; Multithreading; Observability; Software development management; Testing;
Conference_Titel :
Microelectronics, 2004. ICM 2004 Proceedings. The 16th International Conference on
Print_ISBN :
0-7803-8656-6
DOI :
10.1109/ICM.2004.1434594
