DocumentCode
3256626
Title
Implementation of high-side, high-voltage RESURF LDMOS in a sub-half micron smart power technology
Author
Zhu, R. ; Parthasarathy, V. ; Khemka, V. ; Bose, A. ; Roggenbauer, T.
Author_Institution
SPS, Motorola Inc., Mesa, AZ, USA
fYear
2001
fDate
2001
Firstpage
403
Lastpage
406
Abstract
55 V high-side RESURF LDMOS has been integrated successfully in 0.35 μm smart power technology by carefully arranging the lateral doping profile. This device has Rds.on×area of 0.55 mΩ.cm 2 with excellent safe operating area. With proper device terminal biasing scheme, this device can also be used as an isolated device. Techniques and issues related to the isolation is considered and discussed
Keywords
doping profiles; isolation technology; power MOSFET; power integrated circuits; 0.35 micron; 55 V; device isolation; high-side high-voltage RESURF LDMOS transistor; lateral doping profile; safe operating area; smart power technology; terminal biasing; Application specific integrated circuits; Computational geometry; Doping profiles; Electric breakdown; Implants; Isolation technology; Logic design; Logic devices; MOS devices; Power integrated circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Power Semiconductor Devices and ICs, 2001. ISPSD '01. Proceedings of the 13th International Symposium on
Conference_Location
Osaka
ISSN
1063-6854
Print_ISBN
4-88686-056-7
Type
conf
DOI
10.1109/ISPSD.2001.934639
Filename
934639
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