A PCM to PWM conversion stage resolution enhancement architecture

This paper proposes a method for increasing the resolution of digital-input pulse code modulation (PCM) to pulse width modulation (PWM) converters without increasing the maximum clock frequency of the system. The overall resolution increase is accomplished by means of a feed-forward path from an error generating stage to an N-bit multiplexer as a control signal. The input to the multiplexer is N sequentially delayed versions of the generated PWM signal, with each delay being an equal fraction of the sample period. The system output pulse edge is then no longer confined to the edge of the clock, but can now exist at any of the 1/N subdivisions through the choice of multiplexer input lines thus yielding an overall N times increase in perceived output resolution. The proposed system can be utilized for increasing the resolution of current designs or to decrease clock frequencies without sacrificing output resolution. The proposed system is extremely robust, in that any deviation from the desired single stage delay will be compensated by same delay occurring on the opposite pulse edge. This results in a shift of the overall pulse train which does not affect the duty cycle and therefore does not affect the signal. Simulations based on SIMULINK are used to verify the system architecture and the theory presented.