DocumentCode
3256851
Title
Security processor for bulk encryption
Author
Ahmed, Zabir ; Rahmatullah, M. Mohsin ; Jamal, Habibullah
Author_Institution
Univ. of Eng. & Technol., Taxila, Pakistan
fYear
2004
fDate
6-8 Dec. 2004
Firstpage
446
Lastpage
449
Abstract
One of the fundamental challenges for the designers of the crypto processors is to provide the bulk encryption for network applications. In today´s ultra-competitive marketplace, the low cost and flexibility for newer algorithms are the key requirements for any crypto processor. This paper describes a programmable security processor with powerful instruction sets to cater for current as well as future security algorithms. The architecture is specially designed and optimized for IPSEC applications, involving authentication, encryption, key generation and digital signature generation/verification. The novel architecture can be used for wire speed security by adding multiple layers of crypto engines.
Keywords
IP networks; cryptography; digital signatures; microprocessor chips; authentication; bulk encryption; cryptoengines; cryptoprocessors; digital signature generation; digital signature verification; key generation engines; programmable security processor; security algorithm; wire speed security; Application specific processors; Authentication; Computer architecture; Costs; Cryptography; Data security; Energy consumption; Engines; Instruction sets; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronics, 2004. ICM 2004 Proceedings. The 16th International Conference on
Print_ISBN
0-7803-8656-6
Type
conf
DOI
10.1109/ICM.2004.1434610
Filename
1434610
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