Analytical modeling of loop self inductance bound for inductance-aware physical synthesis

An analytical model of loop self inductance bound has been developed that is applicable to a wide range of layout geometries commonly encountered in high performance integrated circuits. When compared with field solver results, the developed model shows an average error of 2.03%. A speedup of more than three orders of magnitude is obtained, enabling our model to be suitable for application in inductance aware physical synthesis. The accurate upper bound of inductance provided by our model can also be used for inductance screening and pre-layout inductance estimation