DocumentCode :
3256922
Title :
Power and ground network topology optimization for cell based VLSIs
Author :
Mitsuhashi, Takashi ; Kuh, Emest S.
Author_Institution :
Electron. Res. Lab., California Univ., Berkeley, CA, USA
fYear :
1992
fDate :
8-12 Jun 1992
Firstpage :
524
Lastpage :
529
Abstract :
A new power and ground network design problem for cell-based VLSIs is discussed. In contrast to the conventional method, the network topology is optimized, or wiring resource consumption subject to electromigration and voltage drop constraints is minimized. The proposed method has been implemented. Using several examples, the validity of the problem formulation and the solution method was confirmed. Experimental results showed that brute power bus enhancement was meaningless and smart power and ground topologies significantly reduced the consumption of wiring resources
Keywords :
VLSI; circuit layout CAD; minimisation of switching nets; cell based VLSIs; network topology optimization; wiring resource consumption; Current density; Energy consumption; Minimization; Network topology; Optimization methods; Rails; Routing; Very large scale integration; Voltage; Wiring;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 1992. Proceedings., 29th ACM/IEEE
Conference_Location :
Anaheim, CA
ISSN :
0738-100X
Print_ISBN :
0-8186-2822-7
Type :
conf
DOI :
10.1109/DAC.1992.227748
Filename :
227748
Link To Document :
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