DocumentCode
325702
Title
Dual Basis Code Design For A Fault-tolerant, Multi-bit Correcting Bus Interface Chip
Author
Redinbo, G. Robert ; Napolitano, Leonard M., Jr. ; Andaleon, David D.
Author_Institution
University of California
fYear
1991
fDate
24-28 Jun 1991
Firstpage
347
Lastpage
347
Keywords
Computer errors; Costs; Error correction; Error correction codes; Fault tolerance; Galois fields; Logic design; Programmable logic arrays; Protection; Reed-Solomon codes;
fLanguage
English
Publisher
ieee
Conference_Titel
Information Theory, 1991 (papers in summary form only received), Proceedings. 1991 IEEE International Symposium on (Cat. No.91CH3003-1)
Print_ISBN
0-7803-0056-4
Type
conf
DOI
10.1109/ISIT.1991.695403
Filename
695403
Link To Document