Coprocessor architecture with scaled dynamic switching activity for embedded cryptosystems

Author

Muresan, Radu ; Xu, Leijian

Author_Institution

Sch. of Eng., Guelph Univ., Ont.

fYear

2005

fDate

7-10 Aug. 2005

Firstpage

1761

Abstract

In embedded cryptosystems, sensitive information can leak via timing, power, and electromagnetic side-channels. In this paper, we introduce a new architecture for cryptographic processors that supports dynamic scaling of the switching activity as a countermeasure against side-channel attacks. The architecture is implemented using CMOSP18 technology. Simulation results based on NANOSIM and SPICE show that desynchronization of current traces is possible and the peak-to-peak variation of the current consumption of the processor is reduced. These effects result in an increased security of a system against side-channel attacks

Keywords

coprocessors; cryptography; embedded systems; leakage currents; switching; CMOSP18 technology; NANOSIM; SPICE; coprocessor architecture; cryptographic processors; desynchronization; embedded cryptosystems; processor current consumption; scaled dynamic switching activity; side-channel attacks; Circuits; Coprocessors; Cryptography; Embedded system; Energy consumption; Field programmable gate arrays; Power engineering and energy; Power supplies; Power system security; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2005. 48th Midwest Symposium on

Conference_Location

Covington, KY

Print_ISBN

0-7803-9197-7

Type

conf

DOI

10.1109/MWSCAS.2005.1594462

Filename

1594462