Coprocessor architecture with scaled dynamic switching activity for embedded cryptosystems

In embedded cryptosystems, sensitive information can leak via timing, power, and electromagnetic side-channels. In this paper, we introduce a new architecture for cryptographic processors that supports dynamic scaling of the switching activity as a countermeasure against side-channel attacks. The architecture is implemented using CMOSP18 technology. Simulation results based on NANOSIM and SPICE show that desynchronization of current traces is possible and the peak-to-peak variation of the current consumption of the processor is reduced. These effects result in an increased security of a system against side-channel attacks