Novel Low-Leakage and High-Speed Triple-Threshold-Voltage Buffers With Skewed Inputs and Outputs

Author

Hong Zhu ; Kursun, V.

Author_Institution

Hong Kong Univ. of Sci. & Technol., Kowloon, China

Volume

61

Issue

7

fYear

2014

fDate

Jul-14

Firstpage

2013

Lastpage

2021

Abstract

Switching speed, active power consumption, standby leakage current, and silicon area are major concerns in buffer design. A new Skewed-IO cell with two split inputs and two split outputs is proposed for low-leakage and high-speed buffer design in this paper. The triple-threshold-voltage buffers with the new Skewed-IO cells offer up to 68.3% and 13.2% reduction in standby leakage currents and propagation delay, respectively, as compared to the conventional static CMOS inverter based buffers under identical load capacitance conditions in a TSMC 65 nm CMOS technology.

Keywords

CMOS integrated circuits; buffer circuits; integrated circuit design; leakage currents; TSMC 65 nm CMOS technology; active power consumption; high-speed buffer design; load capacitance conditions; low-leakage buffer design; propagation delay; silicon area; size 65 nm; skewed-IO cell; split inputs; split outputs; standby leakage current; static CMOS inverter based buffers; switching speed; triple-threshold-voltage buffers; CMOS integrated circuits; CMOS technology; Inverters; MOSFET; Propagation delay; Short-circuit currents; Battery lifetime; energy efficiency; multi- $V_{t}$ CMOS technology; propagation delay; subthreshold leakage currents; tapered buffer;

fLanguage

English

Journal_Title

Circuits and Systems I: Regular Papers, IEEE Transactions on

Publisher

ieee

ISSN

1549-8328

Type

jour

DOI

10.1109/TCSI.2014.2304661

Filename

6766280