A novel current-mode incremental signaling for high-speed parallel links in 0.13 μm CMOS

A novel current-mode incremental signaling scheme for high-speed parallel links is presented. Only N + 1 physical paths are needed for N parallel signal channels. The proposed signaling scheme possesses the intrinsic advantages of current-mode signaling including high data rates, large signal swing, low power consumption, and low substrate noise injection. A new transimpedance amplifier that offers the key advantages of low and tunable input impedance for channel on-chip termination, large bandwidth, and sufficient transimpedance gain is also proposed. A 4-bit parallel link utilizing the proposed signaling scheme has been implemented in UMC 0.13 μm, 1.2V CMOS technology and analyzed using Spectre from Cadence Design Systems with BSIM3.3V device models. Simulation results demonstrate that the proposed signaling scheme is capable of transmitting parallel data, at 10 Gbps.