DocumentCode :
3257507
Title :
On efficient concurrent fault simulation for synchronous sequential circuits
Author :
Lee, Dong Ho ; Reddy, S.M.
Author_Institution :
Iowa Univ., Iowa City, IA, USA
fYear :
1992
fDate :
8-12 Jun 1992
Firstpage :
327
Lastpage :
331
Abstract :
The authors report on an efficient fault simulation method for synchronous sequential circuits. The method is based on concurrent fault simulation and has the simplicity of deductive fault simulation. Several new ideas to reduce computation time and memory requirements are proposed. New fault simulators were developed to simulate transition faults as well as stuck-at faults. The experimental results demonstrate that the proposed method is effective for simulating faults in large synchronous sequential circuits in the workstation environment
Keywords :
fault location; logic CAD; sequential circuits; computation time; concurrent fault simulation; memory requirements; stuck-at faults; synchronous sequential circuits; transition faults; workstation environment; Circuit faults; Circuit simulation; Circuit testing; Cities and towns; Computational modeling; Computer science; Computer simulation; Propagation delay; Sequential analysis; Sequential circuits;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 1992. Proceedings., 29th ACM/IEEE
Conference_Location :
Anaheim, CA
ISSN :
0738-100X
Print_ISBN :
0-8186-2822-7
Type :
conf
DOI :
10.1109/DAC.1992.227784
Filename :
227784
Link To Document :
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