• DocumentCode
    3257529
  • Title

    A new hierarchical layout compactor using simplified graph models

  • Author

    Kim, Wonjong ; Lee, Joohack ; Shin, Hyunchul

  • Author_Institution
    Dept. of Electron. Eng., Hanyang Univ., Seoul, South Korea
  • fYear
    1992
  • fDate
    8-12 Jun 1992
  • Firstpage
    323
  • Lastpage
    326
  • Abstract
    A new hierarchy-preserving hierarchical compactor which can be used with either 1-D or 2-D leafcell compaction techniques has been developed. The compactor is applicable to hierarchical layouts which consist of a number of arrays of identical cells. The hierarchy is maintained throughout the compaction process so that all the instances of a subarray of identical cells have the same shape after compaction. A hierarchical compactor based on the suggested simplified graph model has been developed and experimental results on several benchmark examples showed that the proposed method was satisfactory
  • Keywords
    circuit layout CAD; graph models; hierarchical layout compactor; hierarchy-preserving; leafcell compaction; Application specific integrated circuits; Compaction; Design automation; Integrated circuit layout; Integrated circuit technology; Libraries; Minimization methods; Routing; Shape; Wire;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 1992. Proceedings., 29th ACM/IEEE
  • Conference_Location
    Anaheim, CA
  • ISSN
    0738-100X
  • Print_ISBN
    0-8186-2822-7
  • Type

    conf

  • DOI
    10.1109/DAC.1992.227785
  • Filename
    227785