Title :
An interpreter for general netlist design rule checking
Author_Institution :
Fraunhofer-Inst. of Microelectron. Circuits & Syst., Duisburg, Germany
Abstract :
A new approach to general netlist design rule checking is presented, which has been successfully applied to design for testability rule checking and electrical rule checking. The core of the checker is an interpreter, which performs operations of a set-based calculus. In combination with hierarchy preprocessing by expansion and netlist pattern matching, the interpreter approach is discussed. The implementation and the results achieved are outlined
Keywords :
design for testability; logic CAD; logic testing; design for testability rule checking; electrical rule checking; general netlist design rule checking; hierarchy preprocessing; interpreter; set-based calculus; Calculus; Circuit testing; Circuits and systems; Coupling circuits; Design for testability; Logic; Manufacturing automation; Microelectronics; Pattern matching; Very large scale integration;
Conference_Titel :
Design Automation Conference, 1992. Proceedings., 29th ACM/IEEE
Conference_Location :
Anaheim, CA
Print_ISBN :
0-8186-2822-7
DOI :
10.1109/DAC.1992.227788