DocumentCode :
3257610
Title :
A SDR architecture based on FPGA for multi-standard transmitter
Author :
Bautista-Contreras, B. ; Parra-Michel, R. ; Carrasco-Alvarez, R. ; Romero-Aguirre, E.
Author_Institution :
Dept. of Electr. Eng., CINVESTAV-GDL, Zapopan, Mexico
fYear :
2013
fDate :
3-5 Dec. 2013
Firstpage :
1266
Lastpage :
1269
Abstract :
This paper presents the architecture and implementation of configurable base-band transmitter for software defined radio system. The proposed architecture is capable of generating data-frames for multiple communications standards. The radio parameters can be adjusted on-the-fly: length of data frame, training scheme, transmitter rate, upsampling factor, modulation type and pulse-shaping filter waveform. The configuration is carried out through an interface module via control words. Additionally, it is possible to operate in both continuous and burst data flow. The architecture was described using Verilog HDL and targeted in Altera Stratix V: 5SGXMA7N1F45C1. The implementation results show a reduced consumption of FPGA resources (≤ 1%) and frequency operation over 224 MHz.
Keywords :
field programmable gate arrays; quadrature amplitude modulation; quadrature phase shift keying; radio transmitters; software radio; Altera Stratix V:5SGXMA7N1F45C1; FPGA resources; Verilog HDL; burst data flow; configurable baseband transmitter; continuous flow; control words; data frame length; data-frames; interface module; modulation type; multiple communications standards; pulse-shaping filter waveform; radio parameters; software defined radio system; training scheme; transmitter rate; upsampling factor; Field programmable gate arrays; Mathematical model; Modulation; Radio transmitters; Registers; Training;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Global Conference on Signal and Information Processing (GlobalSIP), 2013 IEEE
Conference_Location :
Austin, TX
Type :
conf
DOI :
10.1109/GlobalSIP.2013.6737139
Filename :
6737139
Link To Document :
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