Functional synthesis using area and delay optimization

The authors present two algorithms that synthesize a netlist of register-transfer level (RTL) components from a functional description while minimizing hardware costs and delay. Functional synthesis is composed of two subtasks, functionality recognition and component mapping, which were incorporated in the functional synthesis algorithms tool (FSA). The two algorithms solve the component mapping problem and accomplish area and delay optimization. The experiments showed that in most cases the algorithms produced a design that was comparable to that of a human designer. It was also found that FSA improved the design quality by 18% in about half of the example runs. FSA was able to improve 66% of the example designs when using functionality recognition by a 42% improvement in design quality