Open the Gates: Using High-level Synthesis towards programmable LDPC decoders on FPGAs

State-of-the-art decoders for LDPC codes adopted by several digital communication standards require a significant amount of hardware resources to achieve the desired high throughput performance. With technology scaling below the 22nm and with billions of transistors available per chip/device, the development cost and complexity of such designs represent an increasing challenge for hardware designers tackling these communication algorithms. This paper proposes a new strategy for developing flexible and totally programmable long-length LDPC decoders to target execution on FPGA devices. We exploit Maxeler´s Java-based technology to describe the LDPC decoder architecture. We compare the performance of this approach with state-of-the-art parallel computing architectures and show that for the most complex family of binary LDPC codes, real-time throughputs in the order of Mbit/s can be achieved with much lower development effort than imposed by RTL descriptions, and with tremendous power savings compared to the powerful GPUs.