Automatic test knowledge extraction from VHDL (ATKET)

The authors describe ATKET (automatic test knowledge extraction tool), which synthesizes test knowledge using structural and behavioral information available in the very high-speed IC description language (VHDL) description of a design. A VHDL analyzer produces an intermediate representation of the information contained in a VHDL design. ATKET interfaces to this intermediate representation to access structural and behavioral information in the design and stores it in suitable data structures. A convenient representation called the module operation tree (MOT) is used to capture the behavior of modules in the design. Information stored in the MOT along with structural information describing connections between modules in the design is used to generate test knowledge. Results obtained from ATKET for a circuit which was difficult to test are presented