A multistage pipelined memory management algorithm for parallel shared memory switches

To resolve the high memory bandwidth requirements presented by output-queued switches, several parallel shared-memory architectures have been recently proposed. The complexity of such systems lies in the algorithms used to assign arriving packets to available shared memories. To date, packet placement algorithms either require N sequential placement decisions per interval or necessitate O(N²) memories, limiting switch scalability and speed. This paper presents a scalable multistage, pipelined memory management algorithm which offers O(logN) computational complexity while requiring only 3N dual-port memories, at a cost of fixed latency